Complementary metal oxide semiconductor (CMOS) devices, such as metal oxide semiconductor field-effect transistors (MOSFETs), are commonly used in the fabrication of ultra-large scale integrated (ULSI) devices. The continuing trend is to reduce the sizes of the devices and to lower the power consumption requirements. As a result, recent trends have been to utilize ultra-shallow junctions in CMOS devices.
For example, NMOS and PMOS transistors typically have a gate insulator and a gate poly formed on a substrate. The substrate, typically a silicon substrate, is doped on either side of the gate to form the source and drain. Electrodes connect to the gate poly, source, and drain. To keep the CMOS devices as small as possible, the CMOS devices are designed such that the source and drain regions and the insulating films are as small as possible, i.e., the CMOS devices are designed with ultra-shallow junctions.
Furthermore, in many cases, pre-doping is performed to implant n-type impurities in an NMOS device or to implant p-type impurities in a PMOS device in the gate poly that forms the gate electrode. Pre-doping improves the threshold voltage and drive current characteristics, thereby further enhancing the performance of the transistor.
However, n-type pre-doping often results in undesired characteristics in the poly-gate profile. Generally, n-type pre-doping is performed by implanting n-type impurities, such as phosphorous, into the gate poly. Mask layers are applied and patterned to etch the gate. The mask layers are removed and an oxidation step is performed. The removal of the mask layer, however, frequently results in a “necking” or “footing” of the gate profile, i.e., the sidewalls of the gate are not vertical, thereby causing device deviation due to inconsistent dopant penetration.
For example, FIG. 1 illustrates a wafer 100 with a gate structure formed thereon after an n-type pre-doping process has been performed. A substrate 110 has a gate insulator 112 formed thereon. A gate 114 is formed on the gate insulator 112, and an oxide layer is formed on the exposed areas of the gate 114 and the gate insulator 112. A neck 118 is formed on the upper portion of the gate 114. The neck 118 induces the n+ dopant to be driven to the n-light doped drain (NLDD) area, which induces poly-finger junction leakage.